This invention relates to semiconductor devices, and more particularly to metallic shorting contacts for MOS integrated circuits (IC's).
Shorting contacts are useful in IC circuits to equalize voltage potentials in two regions of opposite conductivity on the chip. In guard band regions on the chip, shorting contacts prevent latchup, provide common ground potential to two regions of opposite conductivity, and aid device performance.
There are basically two widely accepted approaches now known in designing a shorting contact. One approach is a nonself-aligned approach and the other is a self-aligned approach. The nonself-aligned method tends to result in large area contacts which take up a lot of space on a chip, but they are usually simpler and therefore potentially less expensive. The self-aligned approach, although consuming less space on the chip, tends to be more complicated and expensive requiring self-aligning masks such as silicon nitride and are typically used only when very high power or very fast voltage switching speeds are required.
Manufacturing tolerances such as line width, minimum size of openings, and alignment tolerances are part of the design rules for a given I.C. process. It is desired to make the device features as small as possible to conserve space. To do so, the minimum design rules must be maintained. What is needed is a shorting contact which conserves space on the surface of the integrated circuit while maintaining a large alignment tolerance between masking layers.